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Intel still leads the pack in the 65-nanometer technology race, but at least three other vendors — Texas Instruments, Xilinx, and AMD — are producing microprocessor or logic devices at 65 nm.
Intel Corp. was first to market for 65 nm, rolling its Prescott microprocessor in January 2006, and the company reached the 90-nm to 65-nm crossover point in June for mobile, desktop and server MPUs. With the opening of Fab 24-2 in Ireland that same month, Intel now has three 65-nm production facilities; the others are Fab 12, in Arizona, and the D1D fab in Oregon. Intel shipped 70 million 65-nm microprocessors in 2006 and is rapidly moving production of associated chip sets to the latest node as well. The company's huge 65-nm lead can be partially attributed to its single-product focus and tremendous financial resources, but Intel deserves credit for an aggressive and well-executed strategy.
Texas Instruments Inc. has been quietly producing 65-nm product for third parties such as Nokia since March 2006 using an ASIC design flow in which TI supplies the physical intellectual property. TI now claims ten 65-nm designs. Its initial sweet spot for 65 nm is the cell phone handset, where its low-power process and associated IP excel. In this low-margin space, cost reduction is paramount and is the principal motivation for adoption of the latest technology node. For TI, the high volumes and somewhat less exacting performance requirements make a low-power process the right one to lead technology development.
Other reasons to lead with low power are the somewhat less complicated designs and faster ramp to volume. For example, the TI-manufactured Nokia baseband processor analyzed by Semiconductor Insights (SI) has a comparatively small die size, of 13.2 mm2, vs. 148 mm2 for Intel's 3-GHz dual-core Xeon processor. Although its own 65-nm wireless products have yet to ship under its brand, TI shipped 8.7 million 65-nm units in '06.
TI shortly will address the high-performance DSP and logic space with a separate 65-nm high-performance technology targeted at its own DSPs and at MPUs like Sun's Sparc. The high-performance (HP) node typically lags the low-power process by nine to 12 months, and as of this writing HP products are still in qualification.
A difference for TI at 65 nm is its increased reliance on outside foundries. TI now has four 65-nm-capable fabs--its own Kfab and DMOS6 as well as foundry capacity at UMC and TSMC. TSMC is just beginning production and will be followed later by Chartered. According to Peter Rickert, platform manager for silicon technology development, TI's foundry partners run completely customized, TI-specific processes to turn out parts that are indistinguishable from TI's internally produced parts.
TI's recent announcement of the closure of its Kfab facility and planned termination of internal process development at the 45-nm node obviously point to much closer cooperation with foundry manufacturers at the 32-nm node and beyond.
Fabless FPGA vendor Xilinx Inc. rolled its 65-nm Virtex-5 family in May, with parts available on the open market in December. Xilinx also employs a multiple-foundry strategy, with production at UMC and Toshiba. In a surprising move, both foundries ramped at the same time and were in production virtually simultaneously, aided by dedicated Xilinx teams at both facilities. Although the two foundry processes are different, they design to a common electrical model, resulting in products that Xilinx claims have virtually identical performance. The Virtex-5 LX50 examined by Semiconductor Insights is produced in an impressive 12-level copper metal, 1-volt core process with extensive use of low-k dielectrics and a die size that tips the scales at 146 mm2.
AMD entered the 65-nm fray in December with open-market availability of its 110-mm2 Athlon 64 X2 dual-core desktop processor. Process innovations include a silicon-on-insulator substrate, a unique mobility enhancement scheme and nine levels of copper metallization.
As of this writing, no TSMC 65-nm product is in evidence. Industry sources said Taiwan Semiconductor Manufacturing Co.'s initial 65-nm "G" process had an insufficient performance advantage and excessive power penalty compared with its 90-nm process. That first process has now been superceded by a "G plus" process, but sources estimate that the revision cost TSMC at least three months of development time.
Taking a step back and looking at 65-nm technology, several common themes emerge. For one, nickel silicide has completely replaced cobalt at 65 nm, enabling reduced silicon consumption in the source/drain regions and better resistivity for narrow-line-width gates.
Meanwhile, mobility enhancement to increase performance without gate scaling began at 90 nm and has been widely adopted at 65 nm. Intel uses selectively grown SiGe source/drain regions in the PMOS devices and tensile liners on NMOS devices. TI uses wafers oriented in the 100 rather than the 110 crystal direction to take advantage of the increased hole mobility this creates. TI added a single tensile stress liner at the 65-nm node. It will be interesting to see what choices were made for its high-performance process technology, which will be available shortly. One would expect additional mobility enhancement.
The 65-nm node marks the first use of mobility enhancement by UMC. Borrowing a page from Texas Instruments, UMC uses a 100-oriented wafer, but its stress liner approach differs.
The most novel approach is AMD's use of embedded SiGe (eSiGe), in which thin SiGe layers extend under the source/ drains to compress the NMOS channel. This is augmented with stress memorization technology and dual tensile liners.
Gate oxides have been only marginally scaled at the 65-nm node to keep gate leakage current to acceptable limits. A return to gate oxide scaling awaits the development of reliable high-k gate dielectrics. These will not appear at the 65-nm node, but based on recent announcements from Intel and IBM, they may be used at 45 nm.
Xilinx's Virtex-5 leverages a triple-gate-oxide technology pioneered at 90 nm. The part uses three gate oxide thicknesses: a thick oxide for the I/O devices, a thin oxide for transistors in the critical speed path and a medium thickness for noncritical areas such as the configuration memory and the pass gate routing transistors. The medium oxide thickness reduces gate leakage, while judicious use of the thin oxide assures high performance. This approach probably only applies to FPGAs, however, where the speed constraints on the configuration memory are relaxed compared with cache memory on a gigahertz MPU.
Most MPU manufacturers chose a less obvious but more attractive solution by significantly increasing the amount of nitrogen incorporated into the gate oxide. Manufacturers have for some time done some modest amount of nitridation of the gate oxide, typically of a few percent. Recent measurements by SI, however, point to unprecedented high values of as much as 20 percent nitrogen for some devices. Not only will the increased nitrogen decrease tunnel current, but it also will increase the effective dielectric constant of the dielectric increasing drive. A further benefit is suppression of boron out-diffusion from a PMOS gate into the channel.
As for the next Moore's Law milestone--45 nm--Intel has already publicly announced its intention to be in production in this year's second half. Time will tell.
Edward Keyes (edward@semiconductor.com is chief technology officer at Semiconductor Insights (Kanata, Ontario). He has a BS in applied physics from the University of Waterloo and an MSEE from Carleton University.
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