Overview:
Clock jitter noise is one of the key contributors to timing failures in nanometer designs. However, without a quantitative way to measure the impact of clock jitter on timing, the designers have been forced to over-design to compensate for possible jitter noise. As designs move toward 90nm and beyond, this method of guard-banding is no longer adequate and the designers are experiencing timing failures in their silicon due to clock jitter noise.

Join Apache Design Solutions to learn how Apache's silicon integrity platform with PsiWinder full-chip clock jitter solution and RedHawk power sign-off tool provide spice-accurate analysis of clock jitter impact on timing, at the full-chip level. Apache will also elaborate on the different causes of clock jitter and the need for analyzing both signal and power supply noise together efficiently.

What Will be Covered:
In this educational webinar, Apache will detail their comprehensive solution to clock jitter analysis and advanced power sign-off. Specifically, the webinar will discuss:

• Causes of clock jitter
• Design and analysis solutions for controlling clock jitter
• Methodology and technology for power sign-off

Only a valid business email address will be accepted for registration.